Disclosed are methods of fabricating a photodetector array or pixel array for manufacturing complementary metal-oxide-semiconductor (CMOS) imagers, and to methods of fabricating CMOS imagers for backside illumination.
Backside illuminated CMOS imagers are known to have an excellent quantum efficiency that can compete with backside illuminated charge-coupled devices (CCDs), as for example demonstrated by K. De Munck et al., in “High performance hybrid and monolithic backside thinned CMOS imagers realized using a new integration process”, IEEE International Electron Devices Meeting, San Francisco, US. December 2006, p 139-142. This excellent quantum efficiency was achieved by providing an epitaxial layer with a graded doping profile (where the graded doping profile provided a built-in electric field that guides the flow of photogenerated electrons (minority carriers) towards the depletion region at the front side), and performing backside Boron implantation and subsequent laser annealing for good backside passivation. However, it was noticed that the cross-talk was large in these backside illuminated CMOS imagers or sensors. About 88% overall signal leakage was observed.
Two approaches of fabricating thinned backside illuminated CMOS imagers exist: a monolithic approach and a hybrid approach. In a monolithic approach, a photodetector array or pixel array and the corresponding readout integrated circuit (ROIC) are produced in a same substrate, and both the pixel array and the ROIC are thinned. In a hybrid approach, the photodetector array is produced separately and hybridly integrated on the ROIC, such that only the photodetector array needs to be thinned. Each pixel of the array is connected to the ROIC by a metal bump, such as an indium bump.
To reduce the crosstalk between pixels (photodetectors) caused by the diffusion of photogenerated carriers between the pixels of backside illuminated imagers, a structure comprising deep trenches filled with highly doped polysilicon between the photodetectors has been proposed (K. Minoglou et al, “Reduction of electrical crosstalk in hybrid backside illuminated CMOS imagers using deep trench isolation”, IITC Conf. San Francisco, June 2008, pp. 139-142). However, it was observed that the presence of the trenches negatively affects the quantum efficiency of the imagers. This is illustrated in FIG. 3, showing the measured quantum efficiency for a device without trenches (solid line) and for a device with trenches (dashed line). This difference in quantum efficiency is much larger than would be expected based on the lower fill factor due to the presence of trenches (leading to about 10% loss in quantum efficiency).